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                                                基于多相濾波的四路并行抽樣算法及實現
                                                2021年電子技術應用第11期
                                                徐 波
                                                中國西南電子技術研究所,四川 成都610036
                                                摘要: 在某型數字信號處理模塊的研制中,需要使用高速A/D對射頻信號進行采樣,但由于系統時鐘生成模塊無法輸出320 MHz時鐘,從而導致該高速A/D無法在320 MS/s采樣率下工作。為解決該問題,首先設置A/D采樣率為960 MS/s,然后在FPGA中對采樣信號進行3倍采樣后得到320 MS/s的采樣輸出。該高速A/D與FPGA采用標準的JESD204B接口,所以在FPGA中利用JESD204B IP核對高速信號進行了1:4串并轉換,再對串并轉換信號進行多相濾波、抽取降樣處理后輸出。首先介紹了課題的背景,然后對信號處理模塊的組成、功能和性能指標進行了簡要的說明,對系統在320 MS/s采樣率下存在的問題進行了深入分析,針對該問題提出了四路并行抽樣算法。并基于該算法,利用MATLAB進行了系統建模并進行仿真,仿真結果與預期一致。選取Xilinx公司的高性能FPGA,并結合系統模型中的低通濾波器參數對電路進行實現,最后搭建數字信號處理模塊與Vivado等軟件工具的軟硬件聯合測試環境進行驗證并給出實驗結果。
                                                中圖分類號: TN47
                                                文獻標識碼: A
                                                DOI:10.16157/j.issn.0258-7998.211460
                                                中文引用格式: 徐波. 基于多相濾波的四路并行抽樣算法及實現[J].電子技術應用,2021,47(11):110-115.
                                                英文引用格式: Xu Bo. The four parallel sampling algorithm based on polyphase filtering and its implementation[J]. Application of Electronic Technique,2021,47(11):110-115.
                                                The four parallel sampling algorithm based on polyphase filtering and its implementation
                                                Xu Bo
                                                Southwest China Institute of Electronic Technology,Chengdu 610036,China
                                                Abstract: In the development of a certain type of digital signal processing module, high-speed AD samples the RF signal, but the clock generation module cannot output the 320 MHz clock, which causes the high-speed AD to work normally at the sampling rate of 320 MS/s. Therefore, in a high-performance FPGA, the signal is first sampled 3 times, and the JESD204B IP core performs a 1:4 serial-to-parallel conversion on the high-speed signal. Finally, the serial-to-parallel conversion signal is subjected to polyphase filtering and down sampling. The article first introduces the background of the subject, then briefly describes the composition, function and performance indicators of the signal processing module, and deeply analyzes the problems existing in the sampling rate of 320 MS/s, and proposes four parallel sampling algorithm for the problem. Based on the algorithm, the system was modeled and simulated by MATLAB, and the simulation results were consistent with expectations. It selects Xilinx′s high-performance FPGA and combines the low-pass filter parameters in the system model to implement the circuit. Finally, the digital signal processing module and the software and hardware joint test environment of software tools such as Vivado are built to verify and give the experimental results.
                                                Key words : polyphase filter;4-way parallel sampling algorithm;decimation

                                                0 引言

                                                    Joe Mitola博士在1992年美國通信系統會議上首次明確提出了可編程或可重構無線電系統的概念。理想的軟件無線電架構如圖1所示,在信號接收側:由天線接收的無線電信號經過低噪聲放大后,利用數模轉換器(ADC)對信號進行數字化處理,數字化處理的信號經過FPGA/DSP等完成數字下變頻、數字濾波、數字解調等信號處理任務后送給控制與接口模塊;在信號發射側:從接口過來的基帶信號會通過FPGA/DSP完成數字調制、數字上變頻和數字濾波等信號處理任務,再經模數轉換器(DAC)變換為模擬信號,最后經功率放大器放大到足夠功率,再由天線發射出去[1]。




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                                                作者信息:

                                                徐  波

                                                (中國西南電子技術研究所,四川 成都610036)




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